Chen Bo, Li Xi, Zhou Xuehai. Model Checking of MARTE/CCSL Time Behaviors Using Timed I/O Automata[J]. Journal of Systems Architecture, v88,p120-125,2018,SCI
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Pre One:Gong L , Wang C , Li X , et al. MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip[J]. IEEE Trans Comput Aided Des Integr Circuits Sys, 2018, 37(11):2601-2612,SCI
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