Gong L , Wang C , Li X , et al. MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip[J]. IEEE Trans Comput Aided Des Integr Circuits Sys, 2018, 37(11):2601-2612，SCI

Pre One:Wan B , Li X , Luo H , et al. Work-in-Progress: TTI: A Timing ISA for LET Model in Safety-Critical Systems[C]. Proceedings - Real-Time Systems Symposium，v2018，p363-365，2017，SCI

Next One:Chen Bo, Li Xi, Zhou Xuehai. Model Checking of MARTE/CCSL Time Behaviors Using Timed I/O Automata[J]. Journal of Systems Architecture, v88，p120-125，2018，SCI